1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication. More specifically, the invention is in the field of fabricating SiGe layers in a BiCMOS process.
2. Background Art
In silicon germanium (“SiGe”) bipolar CMOS (“BiCMOS”) technology, SiGe heterojunction bipolar transistors (“HBT”) and CMOS transistors are concurrently fabricated in a single semiconductor die. Fabricating SiGe HBTs requires forming, among other things, a collector, isolation regions and a base. During formation of a SiGe HBT in a SiGe BiCMOS device, a SiGe layer is deposited over the collector and isolation regions to form, respectively, a single crystal SiGe base and a SiGe polycrystalline layer contacting the single crystal SiGe base. It is noted that such SiGe layer deposition is termed “nonselective,” since a blanket SiGe layer is deposited in a “nonselective” manner over the entire surface of the die, but the structure of the SiGe layer will depend on the material it is deposited over. In particular, a single crystalline SiGe layer grows over the collector, whereas a polycrystalline (“poly”) SiGe layer grows over the shallow trench isolation (“STI”) regions—where the SiGe layer conventionally forms large poly grains. As stated above, the poly SiGe thus formed is typically utilized for electrical connection to the single crystal SiGe base of the HBT.
Disadvantageously, SiGe layers comprising large poly grains result in areas of increased surface roughness and “non-continuities” due to voids between the large poly grains. These areas and non-continuities reduce electrical conductance because current must find a path around them. Also, non-continuities due to existence of the large poly grains result in reduced protection of underlying layers, such as the underlying CMOS structures, during etching steps associated with a BiCMOS process.
Therefore, a need exists in the BiCMOS technology for fabricating SiGe layers having small poly grains, which result in increased continuity and decreased surface roughness, which increase conductivity and decrease potential damage to CMOS structures during etching steps in a BiCMOS process.